The present invention relates to semiconductor structures and methods of fabricating the same. More particularly, the present invention relates to planar and non-planar complementary metal oxide semiconductor (CMOS) devices having multiple tuned threshold voltages.
Advanced semiconductor chips employ multiple types of field effect transistors (FETs) having different threshold voltages, on-current per unit width and off-current per unit width. Field effect transistors having a high threshold voltage (on the order of 0.25 V or greater) are typically called “low power” devices, which have a low on-current and a low off-current. Field effect transistors (FETs) having a low threshold voltage (on the order of less than 0.25 V) are called “high performance” devices, which have a high on-current and a high off-current. By employing a mixture of low power devices, and high power devices, a semiconductor chip may provide optimal performance at an optimal power consumption level. In addition to power constraints, several threshold voltages are required to serve several functionalities on the semiconductor chip. Logic devices are typically tuned towards the band edge, while SRAM devices typically require mid-gap threshold voltages.
There are many different techniques to implement multiple threshold voltage devices including, for example, by varying the gate oxide thickness, doping densities, channel lengths and by changing the gate metals. However, these prior art techniques require separate sets of masks and processing steps to form devices of various threshold voltages. As a result, prior art processes of fabricating multiple threshold devices incur additional fabrication costs and complexity.
In addition to the above, it is possible to realize multiple threshold devices of the same physical dimensions and properties by modulating the biases applied to their bodies. However, these devices have a slower operation speed, due to time needed to charge their bodies and wells. Moreover, these prior art techniques may not be applicable to devices with fully depleted bodies.
Many of the prior art techniques for fabricating multiple threshold voltages devices such as those discussed above while applicable for planar semiconductor devices are not applicable to non-planar semiconductor devices and multiple gate devices such as, for example, FinFETs, trigate FETs or any such variety of MUGFETs (multiple gate FETs). As such, there is a need for providing a simple and cost efficient method for fabricating multiple tuned threshold voltage devices that are applicable for non-planar semiconductor devices as well as planar semiconductor devices.